PLECS Real-Time Box

The PLECS RT Box is a state of the art real-time simulator. With its 32 analog and 64 digital input/output channels and its 1 GHz dual-core CPU it is a versatile processing unit for both real-time hardware-in-the-loop (HIL) testing and rapid control prototyping.


1) Hardware-in-the-Loop

When the RT Box is used for HIL testing it typically emulates the power stage of a power electronic system. The power stage could be a simple DC/DC converter, an AC drive system or a complex multi-level inverter system. The device under test (DUT) is the control hardware that will be connected to the RT Box. In such a set-up, the complete controller can be tested without the real power stage.

The inputs of a controller are mostly analog signals coming from voltage and current sensors. In a HIL simulation, these signals are provided by the analog output channels of the RT Box. Other inputs of the controller might be digital, such as speed measurements with Hall effect sensors. Those controller inputs would be connected to digital output channels of the RT Box.

In power electronic applications, the controller generates numerous PWM signals to control the individual power semiconductors. The PWM signals can be captured by the digital inputs of the RT Box with a time resolution of less than 10 ns. Using the captured input data, the RT Box simulates the power stage and provides the simulation results a few microseconds later at its analog outputs. With such a low I/O latency, the controller in fact “thinks” it is controlling a real converter system.

2) Rapid Control Prototyping

Alternatively, the RT Box can be used as a controller for the power stage. In this case, the voltage and current sensors will be connected to the analog inputs of the RT Box. The digital outputs are used to generate high-fidelity PWM signals for the power semiconductors. As the RT Box has more analog and digital channels than most MCUs, as well as higher sampling rates and a faster CPU, you will benefit from substantially higher performance compared to a more integrated controller solution.

If you have two RT Boxes you can connect them back-to-back for full system testing. One RT Box would simulate the power stage and the other one would function as the controller.

PLECS Integration

The RT Box operates hand-in-hand with a host computer running PLECS Standalone or PLECS Blockset and the PLECS Coder. The PLECS Coder translates a PLECS model into real-time capable C code to be compiled for running on the RT Box. The original PLECS model on the host computer can be connected to the simulation on the RT Box using an External Mode. This allows the user to visualize simulation results from the RT Box in the PLECS Scope and to tune parameters on the fly.

Configuration and Comparison

Inside the RT Box 

  • ProcessorAt the heart of the RT Box operates a Xilinx Zynq system-on-chip that consists of an FPGA and 2 CPU cores. The tight integration between the FPGA and CPU allows for ultra-low latency when moving data between the I/O channels and the CPU. One of the CPU cores is used for the real-time simulation while the other core performs communication with the user.
  • Analog I/O:The ADCs and DACs in the RT Box both feature 16 bit resolution at a maximum sample rate of 2 Msps. The inputs and outputs can be adjusted to common industrial voltage ranges. All I/Os are protected against ESD, short circuiting and accidentially applied overvoltages.The analog inputs are differential to suppress common mode EMI. If needed, they can be operated in a single-ended manner.
  • Digital I/O:The digital I/Os are typically used for high-fidelity PWM capture and PWM generation, but can also provide general purpose I/O functionality. They are compatible with 5 V and 3.3 V signal levels.


PLECS RT Box uses SOC to optimize I/O latency, numerical speed and modeling flexibility. An excellent digital signal resolution is achieved using an analog digital converter (ADC) and a digital-to-analog converter (DAC) chip with 2 megasamples per second of the latest 16-bit technology. The digital capture module acquires the PWM signal at 7 ns sampling intervals.

Technical Specifications

Processor Xilinx Zynq Z-7030 1 GHz
Analog inputs Channels 16, simultaneous sampling
Resolution 16 bit
Voltage ranges -10 … 10 V
-5 …   5 V
Input type Differential
Sample rate 2 Msps, no cycle latency
Input impedance 1 MΩ, 24 pF
Connector D-SUB 37 pin male
Analog outputs Channels 16, simultaneous sampling
Resolution 16 bit
Voltage ranges -10 … 10 V
0 … 10 V
-5 …   5 V
0 …   5 V
Sample rate 2 Msps, no cycle latency
Output impedance 0 Ω
Output current ≤ 5 mA
Connector D-SUB 37 pin female
Digital inputs Channels 32
Logic levels 3.3 V (5 V tolerant)
Connector D-SUB 37 pin male
Digital outputs Channels 32
Logic levels 3.3 V
5 V
Connector D-SUB 37 pin female
I/O protection Short-circuit Permanent
Overvoltage -24 … 24 V
Connectivity Ethernet RJ-45, Gigabit
High speed interconnect 4 x SFP+
6.25 Gbps per lane
USB device USB 2.0 high speed, type A
Host PC USB 2.0, type B
Firmware SD card
Power supply Internal 100 … 240 Vac
50 … 60 Hz
50 VA
Size D x W x H 310 x 250 x 100 mm